1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device, specifically to a method of erasing the device, which is able to assure the erase level of memory cells in a NAND cell unit.
2. Description of the Related Art
A NAND-type flash memory is well known as one of electrically rewritable and non-volatile semiconductor memories (EEPROMs). In the NAND type flash memory, there is prepared a floating gate (FG) surrounded by an insulating film disposed between a word line and a p-type well on a semiconductor substrate. Although a charge trap layer may be used in place of the floating gate, the floating gate type of memory cells will be explained in the following description. Control the charge amount in the floating gate, and the threshold voltage of the memory cell may be controlled, so that the different threshold voltage states may be stored as data.
In a data write or program mode of the NAND-type flash memory, a p-type of cell well is applied with 0V; and a selected word line is applied with write or program voltage Vpgm. Under the condition, electrons are injected into the floating gate of a selected memory cell by FN tunneling. That is, the selected cell in an erase state with a negative threshold voltage is selectively written into a positive threshold state.
Data erase is performed by a block. In this erase mode, all word lines in a selected block are set at 0V or near it; and the p-type well is applied with erase voltage Vera. With this voltage application, electrons stored in the floating gates are discharged. In this erase mode, it is in need of performing erase-verify read for verifying whether the cells in the selected block are set under a certain negative threshold state or not.
One problem in the NAND-type flash memory, which is generated in accordance with the progress of cell shrinking and integration, is in that the influence of capacitive coupling between cells becomes large. Specifically, in a write mode or an erase mode, cells disposed adjacent to the select gate transistors are set under a bias condition different from that in the remaining cells due to the influence of capacitive coupling. Therefore, there is generated a certain variation with respect to the write threshold level or erase threshold level (for example, refer to JP-A-2004-127346).
Explaining in detail, there is generated such a problem in a write mode that cells adjacent to the select gate transistors are erroneously written due to GIDL (Gate-induced Drain Leakage) current. Further, in an erase mode, cells adjacent to the select gate transistors may be erroneously judged as passed, in spite of that the threshold level is higher than a suitable value, due to the influence of capacitive coupling from the select gate transistors.
For example, as shown in JP-A-2004-127346, some measures for the above-described threshold variation have been provided as useful ones as follows: cells adjacent to the select gate transistors serve as dummy cells, which are not used for storing data; and these cells adjacent to the select gate transistors are used under a bias condition different from that of other cells.
However, as the cell shrinking and integration are more advanced, there is generated another problem even if the cells adjacent to the select gate transistors are dealt with dummy cells. That is, while repeatedly writing or erasing the memory device, the threshold level of the dummy cells is gradually increased to be high, and it causes erroneous read.